1. Field of the Invention
The present invention relates generally to logic element design, and more particularly, to a hysteresis-based logic element design for improved soft error rate with low area/performance overhead.
2. Introduction
With technology scaling and the associated reduction in the critical charge of a cell, logic designs are getting more susceptible to single event upsets. Although arrayed memory cells can be protected with ECC or other error detection/correction schemes, protecting flip-flops against single event upsets can be difficult.